1. Field of Invention
Embodiments of the invention relate in general to improved electronic packaging. More specifically, the embodiments of the invention relate to a System-in-Package module having adjustable delay lines for improved timing margin.
2. Description of the Background Art
The System-in-Package (SiP) concept combines one or more electronic requirements of a fully functional system or subsystem in one electronic package. The package forms a functional block or module that can be used as a standard component in circuit board level manufacturing. SiP modules enable high-density circuit board layouts by combining one or more integrated circuit (IC) devices, on the same package substrate. This results in considerable savings in the area of circuit boards that would otherwise be dedicated to routing traces between separate packages. It also reduces power consumption because shorter un-terminated wirings (transmission lines) do not need to be terminated.
However, one problem with mounting IC devices in a SiP module arises because the setup and hold times are violated when a synchronous clock signal path is shorter than the original design specification. This may occur because the original design guidelines of the IC devices assumed each of the chips would be packaged in separate packages which necessarily results in a rather long trace from the clock source to devices that use the clock.
To illustrate, consider a SiP module having two IC devices, one of which is a Fast Cycle Random Access Memory (FCRAM) and the other of which is an Application Specific Integrated Circuit (ASIC), having control circuitry including a synchronous clock signal that controls the operation of the FCRAM. If each of these IC devices were originally designed to be mounted on a circuit board, then mounting them on the SiP module will cause setup and hold time violations due to the decrease in spacing and the trace lengths between the IC devices. For example in a typical circuit board where each IC device is separately packaged, a clock line may belong than the trace of the data lines to ensure that the clock signal arrives a few nanoseconds after a data transition. To achieve the delay, it is common practice to layout the circuit board with a longer clock trace which is typically in a serpentine pattern. Thus, the delay time for the clock signal is dependent on the relative length of clock trace relative to the length of the data traces. To illustrate, a serpentine clock trace of about 6 inches is required to implement a half-bit delay at a clock rate of about 250 MHz.
Unfortunately, in the SiP module, routing space for implementing serpentine traces is simply not available. Therefore, in the traditional approach to adapt SiP modules to accept existing IC devices, clock delays must be implemented with thin-film delay lines. Unfortunately, SiP modules with the thin-film delay lines must be custom designed and manufactured for each specific IC chip which is very expensive and requires a long lead time for such custom packages to be built. One will appreciate that custom packages also complicate the manufacturing process because of procuring and stocking requirements. Further, the use of internal delay lines increases the size of the SiP module thereby limiting the advantages of moving IC devices from individual packages to the SiP module. Further still, if the module is to operate at a different clock rate, then a new module must be provided with the appropriate delay lines.
Alternatively, compensation for the shorter transmission delay in the SiP module can be accomplished with a re-spin of the ASIC to add the delay internal to the IC chip. However, this alternative is clearly undesirable due to the cost and time required to redesign the chip layout.